1. Technical Field
Various embodiments relate to a self-repair device, and more particularly, to a technology for improving the repair efficiency and reducing the area of a semiconductor device including a fuse array.
2. Description of Related Art
In general, a semiconductor memory device includes a is number of memory cells. As processing technologies have been developed and thus the degree of integration is augmented, the number of memory cells gradually increases. If a fail occurs in even any one among memory cells, a corresponding semiconductor memory device mis-operates. Therefore, since the semiconductor memory device including a failed cell cannot perform a desired operation, it should be discarded.
However, recently, as processing technologies for manufacturing semiconductor memory devices have been further developed, fails occur probabilistically in only a small number of memory cells. When considering the yield of a product, it is inefficient to discard entire semiconductor memory devices as failed products due to a small number of fails. Thus, in order to cope with this problem, not only normal memory cells but also redundancy memory cells are provided in a semiconductor memory device.
That is to say, a redundancy control circuit is used to perceive in advance the occurrence of a fail through a test and then convert connection to a cell where the fail has occurred into connection to a cell included in a redundancy circuit, when an access to the corresponding cell is requested. The redundancy circuit refers to a set of redundancy memory cells which are separately prepared in addition to normal memory cells and are used as replacement cells of cells in which fails occur.
Redundancy memory cells form a circuit which is provided to is repair failed memory cells (hereinafter, referred to as “memory cells to be repaired”) in the case where fails occur in normal memory cells.
In detail, for example, in the case where a memory cell to be repaired is accessed in read and write operations, not the memory cell to be repaired but a memory cell which operates normally is internally accessed. The memory cell accessed in this way is a redundancy memory cell.
Accordingly, when an address corresponding to a memory cell to be repaired is inputted, a semiconductor memory device performs an operation (hereinafter, referred to as “a repair operation”) for accessing not the memory cell to be repaired but a redundancy memory cell. Through such a repair operation, the semiconductor memory device is ensured with a normal operation.
In order to perform the repair operation, a semiconductor memory device needs not only redundancy memory cells but also other circuit configurations. One of these circuit configurations is a repair fuse circuit. The repair fuse circuit is to store an address corresponding to a memory cell to be repaired (hereinafter, referred to as “an address to be repaired”).
The repair fuse circuit programs an address to be repaired, to fuses. A semiconductor device performs the repair operation using the address to be repaired, which is programmed in this way.
As a net die increases and it is complicated to realize a column redundancy control circuit, an existing self-repair device is performs only a row repair operation. According to this fact, since it is impossible to repair a column-related fail, a repair success rate becomes poor.
Also, in a conventional self-repair device, in order to perform a self-repair operation, an ARE (array rupture electrical fuse) array reads the fuse regions of respective banks. After partial fuse sets which have not been used in the fuse regions are loaded in advance on fuse registers, a memory is tested.
If a failed address occurs as a result of a test, a fuse register of a bank corresponding to the failed address selects a fuse set stored therein and transmits the selected fuse set to the ARE array, and then a repair operation is performed. In this regard, in order to store the information of fuse sets, a number of fuse registers are needed for the fuse regions of the respective banks.